1. Field of the Invention
The present invention relates to a test timing condition setting program automatic generator for automatically generating a test timing condition setting program which defines a test timing condition of a test program for a semiconductor device.
2. Description of the Background Art
FIG. 1 is a flowchart showing conventional programming steps of a test program for testing a semiconductor device. In Step S1, product standards (product specifications) are prepared. Among those included in the product standards is, for example, the product standards include a maximum allowable time or a minimum allowable time from the start of a fall of a RAS signal to the start of a fall of a CAS signal if a semiconductor device to be tested is a memory IC. Next, an engineer generates a product inspection specification sheet in accordance with the product standards (Step S2). The product inspection specification sheet is used in inspecting a device to ensure that the device satisfies the product standards. Therefore, the product inspection specification sheet defines various specifications including test items, test patterns for the respective test items, test timings, voltage conditions and which pin to designate,
In line with the contents of the product inspection specification sheet, the engineer carries out coding (Step S3) and editing (Step S4) to write a source program (Step S5). A source program is a test program for testing a semiconductor device and is written in a high-level language. To code is to write a source program on a desk, and to edit is to key the source program from a terminal component of a computer.
In Step S6, the source program is compiled by a compiler; in other words, the source program written in a high-level language into a program written in a computer language is translated so as to make it acceptable to the testing machine of a semiconductor device (semiconductor tester). By thus compiling the source program, an object program is produced (Step S7). Through the compiling, it is possible to find some of programming errors, if not all, in the source program such as an editing error. Programming errors, if any, are rectified by re-editing alone or re-coding and re-editing in combination in this order.
The test program has not been completed yet even though the object program of the test program is thus produced by compiling, because chances cannot be denied that the object program will not normally function precisely as it should. To eliminate this uncertainty thereby completing the test program, the object program is usually debugged (Step S8). That is, the engineer lets the test program to run on an actual device (semiconductor tester), finds a programming error, and removes the error. In most cases, correction of programming errors found during debugging must be made to the source program. This means another round of programming error correction being required to complete the test program in the form of the object program: re-coding and re-editing thereby correcting the source program, followed by re-compiling of the corrected source program.
In the field of semiconductor devices, memory ICs especially, recent years have seen rapidly increasing needs for higher degree of integration and diversification of products. To catch up with the change due to the acute integration and diversification, test programs for testing such devices must be revised more frequently than before. On the other hand, as described above, a test program requires manual labor of a programming engineer except for compiling. As a result, the semiconductor industry is now being challenged by serious shortage of programming engineers of a test program. To add to the difficulty, a test program which is becoming increasingly complicated inevitably includes a number of programming errors.
To deal with these problems, various systems for automatically generating a test program have been proposed and some of them are already in the process of actual development. However, since some types of semiconductor devices, memory ICs in particular, require an extremely complicated test program, such semiconductor devices as memory ICs are rather behind the other types of semiconductor devices which demand a less complicated test program in development of automatic test program generating systems. A test program for a memory IC is roughly divided into a main program and a sub program. The sub program consists of a test pattern program, a test timing condition setting program, a voltage condition program and a pin designation program, and are under the control of the main program. Among the four programs of the sub program, the test timing condition setting program which defines a test timing condition of the test program needs revision most frequently and takes a quite long programming time.